1. Field of the Invention
This invention relates to a substrate structure of flip chip package, and more particularly to a substrate structure of flip chip package that can improve the bondability of the bump.
2. Description of Related Art
The Flip Chip technology being a package technology frequently applied in the CSP (Chip Scale Technology) can diminish the packaging area and shorten the path of signal transmission through the bump attachment to a carrier since the Flip Chip technology can employ area array for the disposition of bonding pads. In the current Flip Chip products, the contact area between the bump and the mounting pad can be changed, thereby, the collapse phenomenon will be affected depending on the extent of coverage of the solder mask over the mounting pad. The conventional mounting pad design can be classified into two categories, that is, SMD (Solder Mask Define) and NSMD (Non Solder Mask Define).
FIG. 1 shows the mounting pad structure of SMD according to a prior art. Most of the Flip Chip package employs laminating board as the substrate of the flip chip package wherein the laminating board is classified into two types, namely, the press type and the build-up type. As shown in FIG. 1, a laminating board 100 is mainly constituted by alternately stacking up a patterned circuit layer and an insulative layer 102. The patterned circuit layer is formed by the use of a copper foil layer for example, through the photolithographic and etching define, while the material for the insulative layer 102 includes xe2x80x9cflame-retardant epoxy-glass fabric composite resinxe2x80x9d (FR-4 FR-5), Bismaleimide-Taiazine (BT) or epoxy etc. A plurality of mounting pads 104 being formed on the exterior surface of the laminating board 100 is acted as connecting point between the laminating board 100 and the chip 110. In the SMD type of substrate, the solder mask layer 106 covers the patterned circuit layer on the exterior surface of the laminating board 100 while exposes only the outer edge portion of the mounting pad 104. A plurality of bonding pad is formed on the active surface 112 of the chip 110, and an UBM (Under Bump Metallurgy) layer 114 is formed on top of the bonding pad, and bumps 116 such as solder bumps are further formed on top of the UBM layer. The solder mask layer 106 and the size of the UBM layer 114 will limit the range of the collapse of the bumps 116. Therefore, the dimension of the pad w opening 108 of the solder mask layer 106 not only can determine the attaching area between the bumps 116 and the mounting pad 104 but also can affect the collapse phenomenon of the bumps 116 and the final height of the bumps 116.
FIG. 2 shows the mounting pad structure of NSMD according to a prior art. As shown in FIG. 1, in the NSMD structure, the solder mask layer 106a exposes completely the whole surface of the mounting pad 104a, and the bumps 116 attaches not only to the top surface 120 but also the side surfaces 122 of the mounting pad 104a. In this way, the contact area between the bump 116 and the mounting pad 104a is increased. At this moment, since a clearance is kept between the bump 116 and the pad opening 108a, thereby, the pad opening 108a of the solder mask layer 106a will neither affect the collapse phenomenon of the bump 116 nor the final height of the bump 116.
No matter whether it is a SMD or a NSMD structure type of bump pad design, there are merits and demerits in their application. As far as the substrate design of the flip chip package is concerned, the SMD design is relatively not easy to generate voids, thereby, the product yield can be improved in the subsequent underfilling process. This is because that there is no clearance between the bump and the solder mask layer after the bump is attached to the bump pad for the SMD design. But the collapse phenomenon of the SMD and the bondability (between the bump and the mounting pad) are poor, thereby, the demand for the coplanarity of the substrate of the flip chip package is relatively rigorous, and the process tolerance is relatively small. This is because that there is no clearance between the bump and the solder mask layer for the SMD design, thereby, the contact area between the bump and the mounting pad is relatively small.
On the contrary, as far as the NSMD design is concerned, since there is a clearance as between the bump and the pad opening, the contact area is relatively large as it includes the ones on the top and side surfaces. Therefore, the collapse phenomenon is relatively good, and the bondability is relatively robust, thus the tolerance for the coplanar error of the substrate of the flip chip package is relatively large. However, in order to avoid the generation of the void in the subsequent underfilling process, the pad opening of the solder mask layer needs to be enlarged properly. As a result, the pitch of the mounting pads needed to be increased to meet this requirement, thus the packaging density becomes lower, and this makes the layout work of the substrate of the flip chip package relatively difficult. Therefore, it is very important to design a mounting pad that has the merits of both the SMD and the NSMD design while has the least demerits of the SMD and the NSMD design.
In the current flip chip products, the layout of the bumps is mainly classified into a peripheral type and a full matrix type. But based on the limitation of the fabrication and design ability, the disposition of the contact points is limited. Take a build-up substrate of a flip chip package having six layers (2+2+2) of laminating board for example, the mounting pads for signal transmission can usually be disposed on the outer loops. While the power contact points, the ground contact points and the dummy contact points are disposed in the inner loop area. As the space available in the inner loop area is quite sufficient, it is quite flexible as far as the design is concerned, thereby, the pitch of the mounting pads in this area is relatively large.
Therefore, it is the one of the objectives of the present invention to provide a substrate structure of flip chip package having both the SMD and NSMD structure, and to improve manufacturing yield through an appropriate arrangement.
It is another objective of the present invention to provide a substrate structure of flip chip package that allows relatively large coplanar error of the bumps and the mounting pads, consequently, the manufacturing tolerance of the flip chip package is increased.
In order to attain the foregoing and other objectives, the present invention provides a substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.
According to a preferred embodiment of the present invention, a plurality of vias are disposed in the insulative layer for electrically connecting to the patterned circuit layers. And the pitch of the first mounting pads is smaller than the pitch of the second mounting pad. Also, the first mounting pads are disposed on the periphery region of the substrate of the flip chip package while the second mounting pads are disposed in the central region of the substrate of the flip chip package. Moreover, the bumps attach only to the top surface of the first mounting pads while attach to both the top surface and side surfaces of the second mounting pads.